FH4-5834 Suppliers and FH4-5834 Datasheet

Search:
a     b     c     d     e     f     g     h     i     j     k     l     m     n     o     p     q     r     s     t     u     v     w     x     y     z     0     1     2     3     4     5     6     7     8     9      
Home>> 29 >>8545 5962-8670408XA  

FH4-5834   Datasheet:

The FH4-5834 is the 12-bit resolution member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti- mized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The FH4-5834 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The FH4-5834s flexible single-supply operating range of 2.7 V to 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 45 mW without a significant degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 25 mW. The FH4-5834 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated bandgap refer- ence have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families. The FH4-5834 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 kΩ output impedance.

FH4-5834   Suppliers:

Functional Description   The FH4-5834 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1. The device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential LVDS compatible outputs.   The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package.

FH4-5834   On stock:

• Ultra high anode sensitivity   up to 107 A/W • Extremely low dark current,   typically 3pA @ 106 gain • Very low equivalent   noise input (down to 10 -17 W) • Very high stability in dark current   (no bursts) • High gain exceeding 108 • Very high dynamic range • Compact dimensions • Wide spectral response through   multiple window materials • High resolution • Fast response time • High immunity to magnetic fields • Rugged design
Single-stage power conversion, input voltage range of 5V to 18V Reduces the number of components and board size by 30% compared with conventional design Supports both floating and grounded secondary designs 90% efficiency vs. typical 75% efficiency of conventional designs Internal open-lamp and short-circuit protections Wide dimming range Supports synchronization among multiple inverter modules Reliable 2 -winding transformer design, eliminates arcing problems Constant frequency, symmetrical, sinusoidal drive
The C1x generations powerful instruction set, inherent flexibility, high-speed number-handling capabilities, reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal solution for many telecommunications, computer, commercial, industrial, and military applications.
The LDTC applications demand powerful I/O capabilities. The FH4-5834 fulfills this with 27 I/O pins dedicated to input and output. These lines are grouped into four ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
 
 Send inquiry/send message
*Part Number:
*Quantity :
*Business Location :
*Email :
Contact Person:
Telephone :
Description:
 
 D56304C  ISD1730PY  KC80E1E475M  UMF21
 644456-2  CS611216A  KUB8823017010  LM3704YCMM-232/NOPB
 MC74HC151D  OPA2543A  QS74LCX541CQ  LQH4N102K04M00-T052
 PC28F256P33B85 S LA8F  CM05X7R392K50AH  HVM14STL  AFL2803R3S
 LT1728ES5-3.3TR  LC4032B-5T44C  SC8744  RH5RL56AA-TR