 |
MAX8687AETG Suppliers and MAX8687AETG Datasheet |
|
|||
| a b c d e f g h i j k l m n o p q r s t u v w x y z 0 1 2 3 4 5 6 7 8 9 | |||
| Home>> 46 >>13676 | CA3100E | ||
MAX8687AETG Datasheet:The new MAX8687AETG series of high current transient suppressors have been specially designed for use in A.C. Line Protection and any demanding applications (AC or DC).They offer superior clamping characteristics over standard S.A.D. technologies by virtue of the Littelfuse Foldbak™ technology, which provides a clamping voltage which is lower than the avalanche voltage (but above the rated working voltage) therefore any voltage rise due to increased current conduction is contained to a minimum, providing the best possible protection level. They can also be connected in series and/or parallel to create very high capacity protection solutions.MAX8687AETG Suppliers:Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is C0.5V. During transitions, inputs may undershoot to C2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from C1V to VCC +1V.MAX8687AETG On stock:Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad®. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.I 4 banks x 4Mbit x 8 organization I High speed data transfer rates up to 143 MHz I Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge I Single Pulsed RAS Interface I Data Mask for Read/Write Control I Four Banks controlled by BA0 & BA1 I Programmable CAS Latency: 2, 3 I Programmable Wrap Sequence: Sequential or Interleave I Programmable Burst Length: 1, 2, 4, 8 and Sequential Type 1, 2, 4, 8 for Interleave Type I Multiple Burst Read with Single Write Operation I Automatic and Controlled Precharge Command I Random Column Address every CLK (1-N Rule) I Power Down Mode I Auto Refresh and Self Refresh I Refresh Interval: 4096 cycles/64 ms I Available in 54 Pin 400 mil TSOP-II I LVTTL Interface I Single +3.3 V 0.3 V Power Supply Figure 3 shows typical connections to provide a nega- tive supply where a positive supply is available. A similar scheme may be employed for supply voltages anywhere in the operating range of +1.5V to +12V, keeping in mind that pin 6 (LV) is tied to the supply negative (GND) only for supply voltages below 3.5V. The SP6642/3 Evaluation Board provides convenient battery clips to connect the input to an AAA Battery. Or, use the VIN and GND posts to directly connect to standard Power Supply binding post outputs. The Input and Output connections are made with raised female pin receptacles which can accommodate easy-hook connection leads for power and meter connections, as well as scope probe hooks and grounds for waveform measurements. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault occurs using the MAX8687AETG or MAX8687AETG, the channel is turned off and a fault signal is sent to FLT as well as to the serial fault-register bit. When a shorted-load fault occurs while using the MAX8687AETG, the channel transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be flagged as a fault. A fault signal is sent to FLT as well as the serial fault register bit. More detail on fault detection operation is presented in the device operation section of this data sheet. |
