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MC74ACT174ML1 Suppliers and MC74ACT174ML1 Datasheet |
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MC74ACT174ML1 Datasheet:Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale. Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are changed from -VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT - REFB). Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation. The reference voltages are trimmed at production so that (VREFT - VREFB) is within 50mV of the ideal value of 1V. It does not include fixed attenuation. The attenuation temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with temperature. VCM provides the common-mode current for the inputs of all four channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of the VCM buffer if loaded externally. Average current drawn from the reference pins in the external reference mode.MC74ACT174ML1 Suppliers:causes the DQ pins to tri-state. Crystal Connection, drives crystal on startup. Crystal Connection for 32.768 kHz crystal. Capacitor supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used.) Battery supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used.) Power 3.0V +20%, -10% Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected. (Connection Optional) Interrupt Output: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. Programmable to either active high (push/pull) or active low (open-drain). Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Ground Unlabeled pins have no internal connection.MC74ACT174ML1 On stock:The MC74ACT174ML1 2.5V differential clock buffer is a user-selectable differential input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The MC74ACT174ML1 can act as a translator from a differential HSTL, eHSTL, LVEMC74ACT174ML1ECL (2.5V), LVMC74ACT174ML1ECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The MC74ACT174ML1 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.The FAULT output is operational only if ENABLE is high. The output state is detected by monitoring the OUTn terminal using a comparator whose threshold is typically 2.5 V. In order to detect open-circuit outputs, a 30 µA current sink pulls the output below the comparator threshold. To ensure correct fault operation, a minimum load of approximately 1 mA is required. The fault function is disabled when in sleep mode, i.e., FAULT goes high and the 30 µA output sinks are turned off. The FAULT output is a switched current sink of typically 60 µA. In the sleep mode, pin 12 (sleep) is tied to pin 9 (+VBOOST). This disables the amplifiers internal reference and the ampli- fier shuts down except for a trickle current of 3 mA which flows into pin 12. Pin 12 should be left open if the sleep mode is not required. Several possible circuits can be built to take advantage of this mode. In Figure 2A a small signal relay is driven by a logic gate. This removes the requirement to deal with the common mode voltage that exists on the shutoff circuitry since the sleep mode is referenced to the +VBOOST voltage. In Figure 2B, circuitry is used to level translate the sleep mode input signal. The differential input activates sleep mode with a differential logic level signal and allows common mode voltages to VBOOST. Along with the Vaddis III decoder, Zoran provides the necessary firmware to the manufacturer to develop a DVD player in the shortest time possible. The firmware can be used as-is or for manufacturers that would like to customize the firmware for their needs, source code is provided for those areas. • Six skew controlled CMOS outputs • Output skew between any two outputs is less than 150 ps • SMBus Serial configuration interface • 2.5 ns to 5 ns propagation delay • DC to 133 MHz operation (Commercial) • DC to 100 MHz operation (Industrial) • Single 3.3V supply voltage • Low power CMOS design packaged in a 16-pin SSOP (Small Shrink Outline Package) |
